An instruction tracing system (ITS) of a processor provides a debug feature, including a control flow trace that can log what instructions are being executed by a processor. The ITS typically produces a sequential log of the instructions executed by a processor by generating packets specifying branch resolution information, including target information of indirect branches. Because return (RET) instructions are usually the most frequent indirect branches, a sizeable portion of the trace output and bandwidth of the ITS is consumed by packets generated by RET instructions. This bandwidth contributes to computational overhead that does not directly solve a problem handled by the processor.